The present disclosure is related to protection circuits and more particularly to semiconductor devices and integrated circuits with electrostatic protection circuits.
Integrated circuits may be used in a variety of applications such as memory, controllers, networking, processing, display, interfacing and other types of applications. Conventionally, integrated circuits may include known circuits to protect them from electrostatic discharge damage. Such a protective circuit may be referenced as an ESD protection circuit.
ESD protective circuits may be disposed at each pad of an integrated circuit. For example, an I/O pad may include clamp devices that may clamp excessive signal levels to supply busses. The supply busses, in-turn, may also comprise conventional by-pass circuits operable to shunt excessive supply signals to other supply lines of the integrated circuit. With such circuits, an excessive level from an ESD event may be shunted to other regions of the integrated circuit and may diffuse the voltage build-up and protect the integrated circuit from any damage.
As the dimensions of semiconductor devices (e.g., MOSFETs) decrease, they may become more vulnerable to ESD. Accordingly, manufactures strive to improve the reliability of these circuits and may additionally strive to enhance the sensitivity of the protective circuits. Additionally, with the reduced geometries, the level of integration for the integrated circuits may increase. These increased levels of integration may result in semiconductor devices having a greater number of interfacing pads—e.g., I/O pads, supply pads, control pads, etc.—to interface the various signals to/from the device. With such increase in the number of interfacing pads, the number of ESD circuits may similarly increase.